1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a recess channel.
2. Description of the Prior Art
Recently, as a design rule of a MOSFET device has been significantly scaled down below 100 nm, a channel length of a semiconductor device is also significantly shortened. If the channel length is shortened, OFF leakage current of the MOSFET device may increase. In order to reduce the OFF leakage current of the MOSFET, it is necessary to increase the ion implantation dose implanted into a channel region. However, such an increase of the ion implantation dose may cause an increase of leakage current in a storage node junction, thereby shortening a data retention time.
Accordingly, the MOSFET device having a planar channel structure represents a limitation to obtain a cell threshold voltage require for a predetermined semiconductor device. For this reason, various studies and research have been actively performed in order to realize the MOSFET device having a recess channel capable of obtaining an effective channel length.
FIGS. 1A to 1D are sectional views illustrating a procedure for fabricating a semiconductor device having a conventional recess channel, and FIG. 2 is a sectional view illustrating a hard mask layer used for forming the conventional recess channel. Herein, FIGS. 1A to 1D are sectional views taken along line I–I′ shown in FIG. 2.
Referring to FIG. 1A, a buffer oxide layer 3 is formed oh a semiconductor substrate 1 having an isolation layer 2 for defining an active layer. Then, a first hard mask layer 4 is formed on the buffer oxide layer 3. The first hard mask layer 4 is made from polysilicon. After that, a photoresist pattern (not shown) is formed on the first hard mask layer 4 to being expose a recess region.
Referring to FIG. 1B, the first hard mask layer 4 and the buffer oxide layer 3 are etched by using the photoresist pattern as an etching mask. Then, the remained photoresist pattern is removed.
Referring to FIG. 1C, predetermined portions of the semiconductor substrate 1 and the isolation layer 1, which are not covered with the first hard mask layer 4 after the first hard mask layer 4 and the buffer oxide layer 3 have been etched, and a substrate active area formed below the buffer oxide layer 3 are etched. At this time, since the first hard mask layer 4 is made from polysilicon, the first hard mask layer 4 is also removed when the substrate active area is etched. After that, the remaining buffer oxide layer is removed.
Referring to FIG. 1D, after forming a gate oxide layer 6 on a resultant substrate, a doped polysilicon layer 7, a tungsten silicide layer 8, and a second hard mask layer 9 are sequentially formed on the gate oxide layer 6. Then, the second hard mask layer 9 is patterned in the form of a gate. After that, the tungsten silicide layer 8, the doped polysilicon layer 7 and the gate oxide layer 6 are sequentially etched by using the patterned second hard mask layer 9 as an etching mask, thereby forming a gate 10.
After that, although it is not illustrated in figures, after forming a spacer at both sidewalls of the gate 10, an ion implantation process is carried out with respect to the substrate 1, thereby forming a source/drain area in the substrate active area formed at both sides of the gate 10 including the spacer. As a result, a MOSFET device having the recess channel can be obtained.
However, the method for fabricating the semiconductor device having the conventional recess channel has problems as follows:
As shown in FIG. 2, the first hard mask layer 4 is etched in such a manner that a gate forming area including an active area 1a corresponding to a recess channel forming area can be fully exposed. In addition, the etching process for the substrate active area is performed with respect to an open area 4a by using the isolation layer 2, which is an oxide layer, as an etching mask.
However, if the etching process is performed by using the isolation layer 2 as an etching mask, as shown in FIG. 1c, a predetermined portion of the substrate adjacent to the isolation layer 2 is not etched due to the profile of the isolation layer 2. Accordingly, a horn A is formed between the isolation layer 2 and a recessed substrate active area, so that a side channel is formed in the MOSFET device, degrading an efficiency of the recess channel. In order to remove the horn A, it is necessary to further perform the etching process. However, in this case, the recess forming process will be complicated due to the additional etching process.
In addition, as shown in FIG. 3, if a mask is misaligned when forming the photoresist pattern for the recess of the channel area, a predetermined portion B of the substrate may be unnecessarily etched, thereby causing the defect of the semiconductor device.